

An Improved Low Phase Noise LC-VCO with
Wide Frequency Tuning Range Used in CPPLL


Xiaofeng Wang, Zhiyu Wang,
Haoming Li, Rongqian Tian,
Jiarui Liu, and Faxin Yu


(1) When MOS transistors of either polarity are used in analog circuits, the connection of the substrate
is not trivial. Please use appropriate transistor symbols including the substrate. See enclosed drawing.
(2) What is the 1/f-noise corner frequency of your MOS transistors? It seems that your equation [3] does not
account for 1/f-noise that may be quite high in MOS transistors. Why do you not use the complete Leeson's
equation that accounts for all noise sources?
(3)What is the exact switch design for the capacitor bank. What are the gate widths of the different
transistors in the oscillaor and in the capacitor bank.
(4) Fig.7 only shows a section of your chip with no bonding pads. Which circuits do you have on the same
chip? How do you decouple the digital-circuitry noise from modulating the analog VCO?
(5) On Fig.8(b) you only plot the output phase noise of a locked PLL. What is the phase-noise performance
of a free-running VCO?



