A debug target connection item that can connect to one or more target processors. The term is normally used when describing the RealView Debugger Connection Control window.
See ARM Developer Suite
Angel is a software debug monitor that runs on the target and enables you to debug applications running on ARM-based hardware. Angel is commonly used where a JTAG emulator is not available.
A word that encodes an operation for an ARM processor operating in ARM state. ARM instructions must be word-aligned.
A processor that is executing ARM instructions is operating in ARM state. The processor switches to Thumb state (and to recognizing Thumb instructions) when directed to do so by a state-changing instruction. See also, Thumb state.
ARMulator is an instruction set simulator. It is a collection of modules that simulate the instruction sets and architecture of various ARM processors.
Asynchronous execution of a command means that the debugger accepts new commands as soon as this command has been started, enabling you to continue do other work with the debugger
ARM-Thumb Procedure Call Standard.
See Call Stack.
Memory organization where the least significant byte of a word is at the highest address and the most significant byte is at the lowest address in the word.
RealView Debugger uses the term board to refer to a target processor, memory, peripherals, and debugger connection method.
#The board file is the top level configuration file, normally called rvdebug.brd, that references one or more other files.
A user-defined point at which execution stops in order that a debugger can examine the state of memory and registers.
This a list of procedure or function call instances on the current program stack. It might also include information about call parameters and local variables for each instance.
A breakpoint that halts execution when a particular condition becomes true. The condition normally references the values of program variables that are in scope at the breakpoint location.
See pop-up menu.
In the context of Integrator, an add-on development board that contains an ARM processor and local memory. Core modules can run stand-alone, or can be stacked onto Integrator motherboards. See also Integrator.
Current Program Status Register. See Program Status Register.
See Debug Communications Channel.
RSD requires the presence of a Debug Agent on the target to handle requests from the RealView Debugger host components to supprt debugging a multithreaded application. The Debug Agent and RealView Debugger communicate with each other using the Debug Communications Channel (DCC). This enables data to be passed between the debugger and the target using the ICE interface, without stopping the program or entering debug state.
A debug communications channel enables data to be passed between RealView Debugger and the EmbeddedICE logic on the target using the JTAG interface, without stopping the program flow or entering debug state.
A deprecated option or feature is one that you are strongly discouraged from using. Deprecated options and features will not be supported in future versions of the product.
Digital Signal Processors are special processors designed to execute repetitive, mathematics- intensive algorithms. Embedded applications might use both ARM processor cores and DSPs.
A 64-bit unit of information
Debug With Arbitrary Record Format. ARM code generation tools generate debug information in DWARF2 format by default. From RVCT v2.2, you can optionally generate DWARF3 format (Draft Standard 9).
Executable and Linking Format. ARM code generation tools produce objects and executable images in ELF format.
A block of logic, embedded in the hardware, that is connected to the address, data, and status signals of the processor. It broadcasts branch addresses, and data and status information in a compressed protocol through the trace port. It contains the resources used to trigger and filter the trace output.
The EmbeddedICE logic is an on-chip logic block that provides TAP-based debug support for ARM processor cores. It is accessed through the TAP controller on the ARM core using the JTAG interface. See also IEEE1149.1.
In the context of target connection hardware, an emulator provides an interface to the pins of a real core (emulating the pins to the external world) and enables you to control or manipulate signals on those pins.
A debug target processor, normally accessed through an access-provider connection.
See Embedded Trace Macrocell.
See Extended Target Visibility.
Part of the debug target interface, execution vehicles process requests from the client tools to the target.
Extended Target Visibility enables RealView Debugger to access features of the underlying target, such as chip-level details provided by the hardware manufacturer or SoC designer.
Software that emulates the action of a hardware unit dedicated to performing arithmetic operations on floating-point values.
A 16-bit unit of information.
Usually used for RTOS aware debugging, Halted System Debug (HSD) means that you can only debug a target when it is not running. This means that you must stop your debug target before carrying out any analysis of your system. With the target stopped, the debugger presents RTOS information to the user by reading and interpreting target memory. See also Running System Debug (RSD).
A breakpoint that is implemented using non-intrusive additional hardware. Hardware breakpoints are the only method of halting execution when the location is in Read Only Memory (ROM). Using a hardware breakpoint often results in the processor halting is completely. This is usually undesirable for a real-time system. See Breakpoint and Software breakpoint.
The IEEE Standard that defines TAP. Commonly (but incorrectly) referred to as JTAG. See also Test Access Port.
A range of ARM hardware development platforms. Core modules are available that contain the processor and local memory.
An IEEE group focussed on silicon chip testing methods. Many debug and programming tools use a Joint Test Action Group (JTAG) interface port to communicate with processors. For further information refer to IEEE Standard, Test Access Port and Boundary-Scan Architecture specification 1149.1 (JTAG).
A protocol converter that converts low-level commands from RealView Debugger into JTAG signals to the processor, for example, to the EmbeddedICE logic and the ETM.
Memory organization where the least significant byte of a word is at the lowest address and the most significant byte. is at the highest address of the word. See also Big-endian.
A JTAG-based tool for debugging embedded systems.
Also known as Context menu. A menu that is displayed temporarily, offering items relevant to your current situation. Obtainable in most RealView Debugger windows or panes by right-clicking with the mouse pointer inside the window. In some windows the pop-up menu can vary according to the line the mouse pointer is on and the tabbed page that is currently selected.
The part of a microprocessor that reads instructions from memory and executes them, including the instruction fetch unit, arithmetic and logic unit and the register bank. It excludes optional coprocessors, caches, and the memory management unit.
Accumulation of statistics during execution of a program being debugged, to measure performance or to determine critical areas of code.
The Program Status Register (PSR) contains information about the current execution context. It is also referred to as Current PSR (CPSR), to emphasize the distinction between it and the Saved PSR (SPSR), which records information about an alternate processor mode.
See Remote Debug Interface.
RealView ARMulator ISS is an instruction set simulator (ISS). It is a collection of modules that simulate the instruction sets and architecture of various ARM processors.
RealView Compilation Tools is a suite of tools, together with supporting documentation and examples, that enables you to write and build applications for the ARM family of RISC processors.
Part of the RealView Debugger product that extends the debugging capability with the addition of real-time program and data tracing. It is available from the Code window.
A JTAG-based debug solution to debug software running on ARM processors.
The Remote Debug Interface (RDI) is an ARM standard procedural interface between a debugger and the debug agent. RDI gives the debugger a uniform way to communicate with: - a simulator running on the host (for example, ARMulator) - a debug monitor running on ARM-based hardware accessed through a communication link (for example, Angel) - a debug agent controlling an ARM processor through hardware debug support (for example, Multi-ICE).
Remote_A is a software protocol converter and configuration interface. It converts between the RDI 1.5 software interface of a debugger and the Angel Debug Protocol used by Angel targets. It can communicate over a serial or Ethernet interface.
See Running System Debug.
Real Time Operating System.
Used for RTOS aware debugging. Running System Debug (RSD) means that you can debug a target when it is running. This means that you do not have to stop your debug target before carrying out any analysis of your system. RSD gives access to the application using a Debug Agent (DA) that resides on the target. The Debug Agent is sheduled along with other tasks in the system. See also Debug Agent (DA) and Halted System debug (HSD).
A scan chain is made up of serially-connected devices that implement boundary-scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain. Processors might contain several shift registers to enable you to access selected parts of the device.
The range within which it is valid to access such items as a variable or a function.
A file specifying a sequence of debugger commands that you can submit to the command-line interface using the include command.
A mechanism whereby I/O requests made in the application code are communicated to the host system, rather than being executed on the target.
A simulator executes non-native instructions in software (simulating a core).
A breakpoint that is implemented by replacing an instruction in memory with one that causes the processor to take exceptional action. Because instruction memory must be altered, software breakpoints cannot be used where instructions are stored in read-only memory. Using software breakpoints can enable interrupt processing to continue during the breakpoint, making them more suitable for use in real-time systems. See also Breakpoint and Hardware breakpoint.
An instruction that causes the processor to call a programmer-specified subroutine. Used by the ARM standard C library to handle semihosting.
Saved Program Status Register. See Program Status Register.
Software Interrupt. An instruction that causes the processor to call a programmer-specified subroutine. Used by the ARM standard C library to handle semihosting.
Synchronous execution of a command means that the debugger stops accepting new commands until this command is complete.
Setting several processors to a particular program location and state, and starting them together.
Stopping several processors in such a way that they stop executing at the same instant.
Logic on a device which enables access to some or all of that device for test purposes. The circuit functionality is defined in IEEE1149.1. See also IEEE1149.1
The target hardware, including processor, memory, and peripherals, real or simulated, on which the target application is running.
Target vehicles provide RealView Debugger with a standard interface to disparate targets so that the debugger can connect easily to new target types without having to make changes to the debugger core software.
Essentially the debugger itself, this contains the basic debugging functionality. TVS contains the run control, base multitasking support, much of the command handling, target knowledge, such as memory mapping, lists, rule processing, including board-files and .bcd files, and data structures to track the target environment.
The port used to access the TAP Controller for a given device. Comprises TCK, TMS, TDI, TDO and nTRST (optional).
One halfword or two halfwords that encode an operation for an ARM processor operating in Thumb state. Thumb instructions must be halfword-aligned.
A processor that is executing Thumb instructions is operating in Thumb state. The processor switches to ARM state (and to recognizing ARM instructions) when directed to do so by a state-changing instruction. See also, ARM state.
A tracepoint can be a line of source code, a line of assembly code, or a memory address. In RealView Debugger, you can set a variety of tracepoints to determine exactly what program information is traced.
The real-time recording of processor activity (including instructions and data accesses) that occurs during program execution. Trace information can be stored either in a trace buffer of a processor, or in an external trace hardware unit. Captured trace information is returned to the Analysis window in RealView Debugger where it can be analyzed to help identify a defect in program code.
In the context of breakpoints, a trigger is the action of noticing that the breakpoint has been reached by the target and that any associated conditions are met. In the context of tracing, a trigger is an event that instructs the debugger to stop collecting trace data, and display the information around the trigger position, without halting the processor. The exact information that is displayed depends on the position of the trigger within the buffer.
A standard for floating-point coprocessors where several data values can be processed by a single instruction.
A watch is a variable or expression that you require the debugger to display at every step or breakpoint so that you can see how its value changes. The Watch pane is part of the RealView Debugger Code window that displays the watches you have defined.
In RealView Debugger, this is a hardware breakpoint.
A 32-bit unit of information.