Register pane

The Register pane displays the content of registers and, in some circumstances, the debugger internal variables and statistics.

The Register pane is tabbed:

• The Core tab displays the core registers for the connected processor, and the current value of the Program Counter (PC), the Link Register (LR), and the Stack Pointer (SP)

• If you are connected to a target with processor-defined standard registers (as specified in the *.bcd files), there are additional tabs to display these registers. For example, if you are connected to an ARM 920T, you see three tabs that display registers for the CP15 coprocessor: CP15, Cache Operations and TLB Operations. For information on processor-specific registers, please refer to the documentation for the processor.

• The Debug tab displays RealView Debugger Internal variables, including semihosting information for all targets other than the localhost connection to RealView ARMulator ISS

• If you are using the localhost connection to RealView ARMulator ISS to simulate a target processor, the Semihost tab displays the semihosting information  

• If you are using the localhost connection to RealView ARMulator ISS to simulate a target processor, the CycleCount tab displays statistics

• If you are using the localhost connection to RealView ARMulator ISS to simulate a target processor, and you have set up a map file, a Mapfile tab displays details. For more information about creating and using a map file, refer to the RealView ARMulator ISS Guide.

In addition to the core registers, and other standard registers for different processor families, you can define new ASIC registers using the Advanced Information sections of your board file (*.brd) or your board/chip definition file (*.bcd). These user-defined registers are displayed in the Register pane in a separate user-defined tab.

 See the RealView Debugger v1.8 Target Configuration Guide, for more details on how to define new registers.

See the RealView Debugger v1.8 User Guide, Working with Debug Views, for more information on processor-defined registers.