RealView
DebuggerThe N, Z, C and V (Negative, Zero, Carry and oVerflow) bits are known collectively as the condition code flags. They can be tested by most instructions to determine whether the instruction is to be executed.
The condition code flags are usually modified by:
execution of a comparison instruction (CMN,CMP, TEQ or TST)
execution of some other arithmetic, logical or move instruction, where the destination register of the instruction is not R15.
In either case, the new condition code flags (after the instruction has been executed) usually mean:
N Is set to bit 31 of the result of the instruction. If this result is regarded as a 2’s complement signed integer, then N=1 if the result is negative and N=0 if it is positive or zero.
Z Is set to 1 if the result of the instruction is zero (which often indicates an equal result from a comparison), and to 0 otherwise.
C Is set in one of four ways:
For an addition, including the comparison instruction CMN, C is set to 1 if the addition produced a carry (that is, an unsigned overflow), and to 0 otherwise
For a subtraction, including the comparison instruction CMP, C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise.
For non-addition/subtractions that incorporate a shift operation, C is set to the last bit shifted out of the value by the shifter.
For other non-addition/subtractions, C is normally left unchanged (but see the individual instruction descriptions for any special cases).
V Is set in one of two ways:
For an addition or subtraction, V is set to 1 if signed overflow occurred, regarding the operands and result as two’s complement signed integers.
For non-addition/subtractions, V is normally left unchanged (but see the individual instruction descriptions for any special cases).